Organic light emitting diode (OLED) display panel and method of forming polysilicon channel layer thereof

ABSTRACT

An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilcon layer to form a polysilicon channel layer.

This application claims the benefit of Taiwan application Serial No.94142373, filed Dec. 1, 2005, the subject matter of which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to an organic light emitting diode(OLED) panel and a method of forming a polysilicon channel layerthereof, and more particularly to an OLED display panel having a dopantatom not selected from the IIIA group and the VA group doped inside apolysilicon channel layer and a method of forming the polysiliconchannel layer thereof.

2. Description of the Related Art

In the conventional process of manufacturing a low temperaturepolysilicon (LTPS) liquid crystal display (LCD) panel and an organiclight emitting diode (OLED) display panel, typically the excimer laserannealing (ELA) technology is used to scan and melt an amorphous silicon(a-Si) layer to form the crystallization of a polysilicon layer. Thepolysilicon layer can be used as a channel layer of a thin filmtransistor (TFT) to improve the electrical performance of the TFT.

According to related literatures, there are two types of defectsaffecting the electrical performance of polysilicon TFT, namely, thegrain boundary trap defect and the interface trap defect. The grainboundary trap defect mainly occurs during the process of melting thecrystallization of an amorphous silicon layer to form a polysiliconlayer. When the ELA technology is used to melt the amorphous siliconlayer to form the crystallization of a polysilicon layer (the technologyis referred as the ELA crystallization technology hereafter), the numberof grain boundary trap defects and the number of interface traps areapproximately equal to 1012 and 1011, respectively. It can be seen fromthe number of defects that the channel quality of the polysilicon layeris greatly affected by the grain boundary trap defects.

In terms of an LTPS LCD, despite defects occur to the channel layer ofthe high efficient TFT manufactured according to the ELA crystallizationtechnology, the TFT, which is merely used as a switch element of pixels,still meets the requirements of the LTPS LCD.

However, when it comes to OLED display panel, the above negative effectof defects can not be neglected. In the active pixel matrix of the OLEDdisplay panel, each pixel TFT drives an organic electroluminescentdevice (OELD) having an anode, a cathode and an organic material layerby a current. The polysilicon layer manufactured according to the ELAcrystallization technology has non-uniformed crystallization anddefects, causing the channel layer of each TFT to have differentcharacteristics. As a result, line mura would occur to the OLED displaypanel, largely deteriorating the display quality of the OLED displaypanel.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide an OLED displaypanel and a method of forming a polysilicon channel layer thereof. Thedesign of disposing a dopant atom not selected from the IIIA group andthe VA group inside the polysilicon layer (such as the polysilicon layerformed according to the ELA crystallization technology) formed byapplying heat treatment to the crystallization of the amorphous siliconlayer uniforms the defects of the polysilicon layer. Therefore, thenon-uniform crystallization and defects of the polysilicon layer can beimproved, so that the polysilicon channel layer of each TFT has the samecharacteristics. As a result, each pixel TFT has the samecharacteristics, preventing the OLED display panel from generating linemura during operation, largely improving the display quality of the OLEDdisplay panel.

The invention achieves the above-identified object by providing an OLEDdisplay panel including a substrate, a pixel and a thin film transistor.The pixel is disposed on the substrate. The thin film transistordisposed inside the pixel includes a polysilicon channel layer. A dopantatom not selected from the IIIA group and the VA group of periodic tablethe is doped inside the polysilicon channel layer.

The invention further achieves the above-identified object by providinga method of forming a polysilicon channel layer. At first, a substratehaving an amorphous silicon layer disposed thereon is provided. Then,heat treatment is applied to the amorphous silicon layer to form apolysilicon layer. Then, a dopant atom not selected from the IIIA groupand the VA group of periodic table is doped inside the polysilcon layerto form a polysilicon channel layer.

The invention further achieves the above-identified object by providinga method of forming a polysilicon channel layer. At first, a substratehaving a first polysilicon layer and a second polysilicon layer disposedthereon is provided. Then, a mask having an opening for exposing thefirst polysilicon layer is used to cover the substrate. Then, a dopantatom not selected from the IIIA group and the VA group of periodic tableis doped inside the first polysilicon layer to form a polysiliconchannel layer.

The invention further achieves the above-identified object by providinga method of forming a polysilicon channel layer. At first, a substratehaving a first polysilicon layer and a second polysilicon layer disposedthereon is provided. Then, a first mask having a first opening and asecond opening for respectively exposing the first polysilicon layer andthe second polysilicon layer is used to cover the substrate. Then, afirst dopant atom not selected from the IIIA group and the VA group ofperiodic table is doped inside the first polysilicon layer and thesecond polysilicon layer to respectively form a first polysiliconchannel layer and a second polysilicon channel layer. The dopingconcentration of the first dopant atom in the first polysilicon channellayer is the same with the doping concentration of the first dopant atomin the second polysilicon channel layer. Then, the first mask isremoved, and a second mask having a third opening for exposing the firstpolysilicon channel layer is used to cover the substrate. Then, a seconddopant atom not selected from the IIIA group and the VA group ofperiodic table is doped inside the first polysilicon channel layer toform a third polysilicon channel layer. The total doping concentrationof the first dopant atom and the second dopant atom in the thirdpolysilicon channel layer is larger than the doping concentration of thefirst dopant atom in the second polysilicon channel layer.

Other objects, features, and advantages of the invention will becomeapparent from the following detailed description of the preferred butnon-limiting embodiments. The following description is made withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a circuit structure of a single pixel of an organiclight emitting diode (OLED) display panel according to a firstembodiment of the invention;

FIG. 2 illustrates a cross-sectional view of detailed structure of thesingle pixel of the OLED display panel according to the first embodimentof the invention;

FIG. 3 is a flowchart of a method of forming a polysilicon channel layeraccording to a second embodiment of the invention;

FIG. 4 is a flowchart of a method of forming a polysilicon channel layeraccording to a third embodiment of the invention;

FIGS. 5A˜5H illustrate cross-sectional views of the manufacturingprocess of a polysilicon channel layer according to the third embodimentof the invention;

FIG. 6 is a flowchart of a method of forming a polysilicon channel layeraccording to a fourth embodiment of the invention; and

FIGS. 7A˜7H illustrate cross-sectional views of the manufacturingprocess of a polysilicon channel layer according to the fourthembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

Referring to FIGS. 1˜2. FIG. 1 illustrates a circuit structure of asingle pixel of an organic light emitting diode (OLED) display panelaccording to a first embodiment of the invention. FIG. 2 illustrates across-sectional view of detailed structure of the single pixel of theOLED display panel according to the first embodiment of the invention.As shown in FIGS. 1˜2, the OLED display panel 10 at least includes asubstrate 11, a pixel 13 and a first thin film transistor (TFT) T1. Thepixel 13 disposed on the substrate 11 is exemplified by one of theseveral pixels of an active matrix pixel array. The first thin filmtransistor T1 disposed inside the pixel 13 includes a first polysiliconchannel layer 14. Apart from a polysilicon, the first polysiliconchannel layer 14 further includes a first dopant atom not selected fromthe III A group and the VA group of periodic table to uniform thedefects of the polysilicon layer before doping. Therefore, thenon-uniformity of the defects and crystallization of the polysiliconlayer can be improved, and the polysilicon channel layer of each pixelTFT can have the same characteristics. As a result, the OLED displaypanel will not generate line mura during operation, largely improvingthe display quality of the OLED display panel and greatly impressing theconsumers.

Examples of the first dopant atom doped inside the first polysiliconchannel layer 14 includes a neutral atom, an inert gas and/or the IVAgroup of periodic table. For example, the first dopant atom is a dopantatom selected from the group consisting of helium (He), neon (Ne), argon(Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any combinationthereof. The first dopant atom is a dopant atom selected from the groupconsisting of carbon (C), silicon (Si), germanium (Ge), tin (Sn) andlead (Pb) and any combination thereof. The first dopant atom can also beselected from the combination of inert gases and the IV A group.However, the technology of the present embodiment of the invention isnot limited thereto. For example, the first dopant atom can be selectedfrom neutral dopant atoms other than the IIIA group and the VA group ofthe periodic table. That is, the first dopant atom is not selected fromthe IIIA group and the VA group of the periodic table. Furthermore, thedoping concentration of the first dopant atom in the first polysiliconchannel layer 14 ranging 10¹¹˜10¹⁵ atoms/cm² can be larger than 10¹²atoms/cm². The above first polysilicon channel layer 14 can be achievedby doping a polysilicon layer with the first dopant atom, and thepolysilicon layer can be achieved by applying heat treatment to anamorphous silicon layer. For example, the amorphous silicon layer can bemelted according to the laser annealing method to form thecrystallization of the polysilicon layer. In the laser annealing method,the amorphous silicon layer is scanned and melted by an excimer laser.

In the process of manufacturing the first thin film transistor T1according to the present embodiment of the invention, at first, theamorphous silicon layer is melted according to the excimer laserannealing (ELA) crystallization technology to form the crystallizationof the polysilicon layer. Then, a fixed amount of first dopant atom isdoped inside the polysilicon layer to achieve the above firstpolysilicon channel layer 14.

In the present embodiment of the invention, the first thin filmtransistor T1 further includes a first gate G1, a first source S1 and afirst drain D1. The first source S1 and the first drain D1 are disposedon the first polysilicon channel layer 14, and are correspondingly andelectrically connected to the two ends of the first polysilicon channellayer 14. The first gate G1 is disposed on the first polysilicon channellayer 14, and positioned between the first source S1 and the first drainD1. The first source S1 and the first drain D1 respectively areelectrically connected to and contact the polysilicon channel layer 14via a heavily doping N type layer (N+).

Moreover, the OLED display panel 10 further includes a first scan lineSL1, a second scan line SL2, a first data line DL1, a second data lineDL2, and a second thin film transistor T2. The first scan line SL1 andthe second scan line SL2 are disposed on the substrate 11 in parallel.The first data line DL1 and the second data line DL2 are disposed on thesubstrate 11 in parallel, and are respectively perpendicular to andalternate with the first scan line SL1 and the second scan line SL2 todefine the pixel 13. The second thin film transistor T2 disposed insidethe pixel 13 includes a second gate G2, a second source S2, a seconddrain D2 and a second polysilicon channel layer 22. The second source S2and the second drain D2 are correspondingly disposed on the two ends ofthe second polysilicon channel layer 22, and are electrically connectedto and ohmly contact the two ends of the second polysilicon channellayer 22 via the N+ layer, respectively. The second gate G2 iselectrically connected to the first scan line SL1. The second source S2is electrically connected to the first data line DL1. The second drainD2 is electrically connected to the first gate G1.

A second dopant atom not selected from the IIIA group and the VA groupis doped inside the second polysilicon channel layer 22. The dopingconcentration of the second dopant atom in the second polysiliconchannel layer 22 is the same or different with the doping concentrationof the first dopant atom in the first polysilicon channel layer 14. Thedoping concentration of the first dopant atom in the first polysiliconchannel layer 14 can be larger than the doping concentration of thesecond dopant atom in the second polysilicon channel layer 22. Examplesof the second dopant atom include a neutral atom, an inert gas and/orthe IV A group. For example, the second dopant atom is a dopant atomselected from the group consisting of helium (He), neon (Ne), argon(Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any combinationthereof. The second dopant atom is a dopant atom selected from the groupconsisting of carbon (C), silicon (Si), germanium (Ge), tin (Sn) andlead (Pb) and any combination thereof. The second dopant atom can beselected from the combination of inert gases and the IVA group. Thefirst dopant atom is the same or different with the second dopant atom.The second dopant atom can be selected from the neutral dopant atomsother than the IRA group and the VA group of the periodic table.Moreover, the above second polysilicon channel layer 22 can be achievedby doping a polysilicon layer with the second dopant atom, and thepolysilicon layer can be achieved by applying heat treatment to anamorphous silicon layer. For example, the amorphous silicon layer can bemelted according to the laser annealing method to form thecrystallization of the polysilicon layer. In the laser annealing method,the amorphous silicon layer is scanned and melted by an excimer laser.

The OLED display panel 10 further includes a storage capacitor Cs and anorganic electroluminescent device (OELD) 25. The storage capacitor Cs isdisposed inside the pixel 13. One end of the storage capacitor Cs iselectrically connected between the first gate G1 and the second drainD2, and the other end of the storage capacitor Cs is electricallyconnected between the first source S1 and a first constant voltage Vdd.The OELD 25 is disposed inside the pixel 13 to be electrically connectedto the first drain D1 and a second constant voltage Vss.

Any one who is skilled in the technology of the present embodiment ofthe invention will understand that the technology of the presentembodiment of the invention is not limited thereto. For example, theOLED display panel 10 further includes an isolation layer 18 disposedamong the first polysilicon channel layer 14, the second polysiliconchannel layer 22 and the substrate 11. Besides, the OLED display panel10 further includes an isolation layer 19 disposed among the first gateG1, the second gate G2 and the first polysilicon channel layer 14.Examples of the isolation layers 18 and 19 include oxide, nitride,nitroxide, nitro-silicon or nitrogen oxide.

The detailed structure of the OELD 25 is exemplified below. However, thetechnology of the present embodiment of the invention is not limitedthereto. The OELD 25 at least includes an anode 26, a cathode 27 and anorganic material layer 28. The organic material layer 28 is disposedbetween the anode 26 and the cathode 27. The anode 26 is electricallyconnected to the first drain D1. The cathode 27 can be grounded orreceive a constant voltage. The organic material layer 28 can include anelectron hole source, an electron source and a light emitting layer. Thelight emitting layer is disposed between the electron hole source andthe electron source. The electron hole source is adjacent to the anode26, and the electron source is adjacent to the cathode 27.

In the present embodiment of the invention, the OLED display panel 10further includes a substrate 21. The substrate 21 and the substrate 11are assembled in parallel by a sealant for sealing and enclosing thepixel 13, the first thin film transistor T1, the second thin filmtransistor T2, the storage capacitor Cs and the OELD 25. Examples of thesubstrates 11 and 21 include glass substrate, plastic substrate, ceramicsubstrate or flexible substrate.

Despite the present embodiment of the invention is exemplified by theTFT structure of the top gate, the technology of doping the polysiliconchannel layer of the present embodiment of the invention with a dopantatom not selected from the IIIA group and the VA group can be applied tothe TFT structure of the bottom gate or the dual gates.

According to the present embodiment of the invention, after theamorphous silicon layer is melted according to the excimer laserannealing (ELA) method to form the crystallization of the polysiliconlayer (the ELA crystallization technology), the original density of thedefects of the polysilicon layer is adjusted by doping the dopant atomnot selected from the IIIA group and the VA group inside the polysiliconlayer to form the polysilicon channel layer. As the doping amount anddensity of the dopant atom not selected from the IIIA group and the VAgroup can be precisely controlled, the characteristics of the TFT can beeffectively controlled accordingly. The uniformity achieved according tothe doping technology improves the non-uniformity of the ELAcrystallization method as well as the line mura effect. The tabledisclosed below illustrates the improvement in the density of defects ofthe channel layer of the OLED display panel. The resulted line mura ofthe entire OLED display panel before the dopant atom not selected fromthe IIIA group and the VA group is doped is compared with the resultedline mura of the entire OLED display panel after the dopant atom notselected from the IIIA group and the VA group is doped. However, thetechnology of the present embodiment of the invention is not limitedthereto. TABLE 1 Area Without Area With Defect Line Mura Line Mura RatioDefect Concentration Before 10¹² 10¹³ 10 Doping (defects/cm²) The Dopingconcentration of 10¹³ 10¹³ 1 the Dopant Atom not Selected from the III AGroup and the VA Group (atoms/cm²) Defect Concentration After 1.1*10¹³2*10¹³ 1.67 Doping (defects/cm²)

It can be seen from Table 1 that in a conventional OLED display panelwithout doping the dopant atom not selected from the IIIA group and theVA group, the defect ratio between the defects of the area with linemura and the defects of the area without line mura is 10:1. In the OLEDdisplay panel of the present embodiment of the invention, after dopingthe dopant atom not selected from the IIIA group and the VA group in thepolysilicon layer, the doping concentration of the dopant atom notselected from the MA group and the VA group increases by 10 times. Thedefect ratio between the defects of the area with line mura and thedefects of the area without line mura is improved from 10:1 to 1.67:1after doping a calculated amount of dopant not selected from the IIIAgroup and the VA group. By doping an appropriate amount of the dopantatom not selected from the IIIA group and the VA group, the channelquality is uniformed so that the polysilicon channel layer of each pixelTFT has the same characteristics and that the non-uniformity of defectsand ELA crystallization of is improved. As a result, each pixel TFT hasthe same characteristics.

With regard to the performance of the OLED display panel under differentdoping densities of the dopant atom not selected from the IIIA group andthe VA group according to the present embodiment of the invention, thedoping concentration of the dopant atom not selected from the IIIA groupand the VA group is 1.5*10¹²/cm² and still has line mura. However, theline mura in the present embodiment of the invention is fewer than theline mura under standard conditions.

When the doping concentration of the dopant atom not selected from theIIIA group and the VA group is 1.5*10¹³/cm², no line mura occurs. Theeffect of line mura can be improved by appropriately adjusting thedoping concentration of the dopant atom not selected from the IIIA groupand the VA group. This is because the performance of the channel qualityis dominated by the effect of doping the dopant atom not selected fromthe IIIA group and the VA group instead of the ELA crystallizationtechnology.

The grain size of the polysilicon layer before doping ranges 0.1˜10 μm.The density of the grain boundary defect of the polysilicon layer islarger than 10¹¹ defects/cm². When the polysilicon layer is within 5 μm,the largest thickness differs with the smallest thickness by more than100 Å, that is, the height of the protrusion of the polysilicon layer,and the density of the first dopant atom not selected from the IIIAgroup and the VA group doped inside the first polysilicon channel layer14 can be larger than 10¹² atoms/cm². Therefore, the present embodimentof the invention, according to the grain size of the polysilicon layer,the density of grain boundary defect, and the height of the protrusionof the polysilicon layer, can appropriately adjust the density of thedopant atom not selected from the IIIA group and the VA group dopedinside the polysilicon layer to form the needed polysilicon channellayer.

Second Embodiment

Referring to FIG. 3, a flowchart of a method of forming a polysiliconchannel layer according to a second embodiment of the invention isshown. As shown in FIG. 3, at first, in the step 31, a substrate havingan amorphous silicon layer disposed thereon is provided. Then, proceedto the step 32, heat treatment is applied to the amorphous silicon layerto form a polysilicon layer. Then, proceed to the step 33, a dopant atomnot selected from the III A group and the VA group is doped inside thepolysilcon layer to form a polysilicon channel layer. Examples of thedopant atom include a neutral atom, an inert gas and/or the IVA group.For example, a dopant atom is selected from the group consisting ofhelium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon(Rn) and any combination thereof, but is not selected from the IIIAgroup and the VA group in the periodic table. The dopant atom is adopant atom selected from the group consisting of carbon (C), silicon(Si), germanium (Ge), tin (Sn) and lead (Pb) and any combinationthereof. The dopant atom can be selected from the combination of inertgases and the IV A group. Besides, the doping concentration of thedopant atom in the polysilicon channel layer ranging 10¹¹˜10¹⁵ atoms/cm²can be larger than 10¹² atoms/cm². Besides, heat treatment can also beapplied to the amorphous silicon layer according to the laser annealingmethod. For example, the amorphous silicon layer is step scanned andmelted by an excimer laser to form the polysilicon layer according tothe ELA crystallization technology.

In the present embodiment of the invention, the design of doping thecrystallization of the polysilicon layer formed by applying heattreatment to the amorphous silicon layer (such as the polysilicon layerformed according to the ELA crystallization technology) with the dopantatom not selected from the IIIA group and the VA group (such as inertgases) enables the defects of the polysilicon layer to be uniformed,improving the non-uniformity of the defects and crystallization of thepolysilicon. Thus, the OLED display panel manufactured in subsequentmanufacturing process will not generate line mura during operation,largely improving the display quality of the OLED display panel.

Third Embodiment

Referring to FIGS. 4˜5H. FIG. 4 is a flowchart of a method of forming apolysilicon channel layer according to a third embodiment of theinvention. FIGS. 5A˜5H illustrate cross-sectional views of themanufacturing process of a polysilicon channel layer according to thethird embodiment of the invention. As shown in FIG. 4, at first, in thestep 41, a substrate 11 having a first polysilicon layer 24 a and asecond polysilicon layer 24 b disposed thereon is provided. As for howthe first polysilicon layer 24 a and the second polysilicon layer 24 bare formed on the substrate 11 is exemplified below. However, thetechnology of the present embodiment of the invention is not limitedthereto. As shown in FIG. 5A, the substrate 11 having an amorphoussilicon layer 23 disposed thereon is provided. Then, heat treatment isapplied to the amorphous silicon layer 23 to form a polysilicon layer 24as shown in FIG. 5B. Here, heat treatment can be applied to theamorphous silicon layer 23 according to the laser annealing method. Forexample, the amorphous silicon layer 23 is step scanned and melted by anexcimer laser 53 along the direction of the arrow 54 in FIG. 5A to formthe crystallization of the polysilicon layer 24 step by step. Then, asshown in FIG. 5C, part of the polysilicon layer 24 is removed form thefirst polysilicon layer 24 a and the second polysilicon layer 24 b.However, the technology of forming the first polysilicon layer 24 a andthe second polysilicon layer 24 b according to the present embodiment ofthe invention is not limited thereto.

After the first polysilicon layer 24 a and the second polysilicon layer24 b are formed on the substrate 11, proceed to the step 42 as shown inFIG. 5D, the substrate 11 is covered by a first mask 51. The first mask51 has a first opening 51 a used for exposing the first polysiliconlayer 24 a.

Then, proceed to the step 43 as shown in FIG. 5E, a first dopant atomnot selected from the IIIA group and the VA group A1 is doped inside thefirst polysilicon layer 24 a to form a first polysilicon channel layer14. Examples of the first dopant atom A1 include a neutral atom, aninert gas and/or the IVA group. The first dopant atom A1 is selectedfrom the group consisting of helium (He), neon (Ne), argon (Ar), krypton(Kr), xenon (Xe) and radon (Rn) and any combination thereof. The firstdopant atom A1 is a dopant atom selected from the group consisting ofcarbon (C), silicon (Si), germanium (Ge), tin (Sn) and lead (Pb) and anycombination thereof. The first dopant atom A1 can be selected from thecombination of inert gases and the IV A group. The doping concentrationof the first dopant atom A1 in the first polysilicon channel layer 14ranges 10¹¹˜10¹⁵ atoms/cm2. In the step 43, the first dopant atom A1 canbe used as a source of dopant to be doped inside the first polysiliconlayer 24 a according to the ion implantation method.

Then, proceed to the step 44 as shown in FIG. 5F, the first mask 51 isremoved, and the substrate 11 is covered by a second mask 52. The secondmask 52 has a second opening 52 a used for exposing the secondpolysilicon layer 24 b.

Then, proceed to the step 45 as shown in FIG. 5G, a second dopant atomnot selected from the IIIA group and the VA group A2 is doped inside thesecond polysilicon layer 24 b to form a second polysilicon channel layer22. Examples of the second dopant atom A2 include a neutral atom, aninert gas and/or the IVA group. The doping concentration of the seconddopant atom A2 in the second polysilicon channel layer 22 is the same ordifferent with the doping concentration of the first dopant atom A1 inthe first polysilicon channel layer 14. The doping concentration of thefirst dopant atom A1 in the first polysilicon channel layer 14 is largerthan the doping concentration of the second dopant atom A2 in the secondpolysilicon channel layer 22. The second dopant atom is a dopant atomselected from the group consisting of helium (He), neon (Ne), argon(Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any combinationthereof. The second dopant atom A2 is a dopant atom selected from thegroup consisting of carbon (C), silicon (Si), germanium (Ge), tin (Sn)and lead (Pb) and any combination thereof. The second dopant atom A2 canbe selected from the combination of inert gases and the IV A group. Thefirst dopant atom A1 and the second dopant atom A2 can be the same ordifferent. In the step 45, the second dopant atom A2 can be used as asource of dopant to be doped inside the second polysilicon layer 24 baccording to the ion implantation method. Then, proceed to the step 46as shown in FIG. 5H, the second mask 52 is removed.

Any one who is skilled in the technology of the present embodiment ofthe invention will understand that the technology of the presentembodiment of the invention is not limited thereto. For example, afterthe first polysilicon layer 24 a and the second polysilicon layer 24 bare formed on the substrate 11, a thin sacrifice layer such as silicondioxide (SiO₂) can be used to cover the first polysilicon layer 24 a andthe second polysilicon layer 24 b. Besides. after the second dopant atomA2 is doped inside the second polysilicon layer 24 b, dilute HF is usedto remove the sacrifice layer. Here, the sacrifice layer can be used asa buffer layer when the first dopant atom A1 and the second dopant atomA2 are respectively doped inside the first polysilicon layer 24 a andthe second polysilicon layer 24 b to mitigate the damage occurring tothe surface of the first polysilicon layer 24 a and the source of thesecond polysilicon layer 24 b when doped with the first dopant atom A1and the second dopant atom A2, respectively.

Fourth Embodiment

Referring to FIGS. 6˜7H. FIG. 6 is a flowchart of a method of forming apolysilicon channel layer according to a fourth embodiment of theinvention. FIGS. 7A˜7H illustrate cross-sectional views of themanufacturing process of a polysilicon channel layer according to thefourth embodiment of the invention. As shown in FIG. 6, at first, in thestep 61, a substrate 11 having a first polysilicon layer 24 a and asecond polysilicon layer 24 b disposed thereon is provided. As for howthe first polysilicon layer 24 a and the second polysilicon layer 24 bare formed on the substrate 11 as shown in FIGS. 7A˜7C is alreadydisclosed in the second embodiment, and is not repeated here.

Then, proceed to the step 62 as shown in FIG. 7D, the substrate 11 iscovered by a first mask 71. The first mask 71 has a first opening 71 aand a second opening 71 b. The first opening 71 a and the second opening71 b are respectively used for exposing the first polysilicon layer 24 aand the second polysilicon layer 24 b.

Then, proceed to the step 63 as shown in FIG. 7E, a first dopant atomnot selected from the IIIA group and the VA group A3 is doped inside thefirst polysilicon layer 24 a and the second polysilicon layer 24 b torespectively form a third polysilicon channel layer 24 c and a secondpolysilicon channel layer 22. Examples of the first dopant atom A3include a neutral atom, an inert gas and/or the IVA group. The dopingconcentration of the first dopant atom A3 in the second polysiliconchannel layer 22 is the same with the doping concentration of the firstdopant atom A3 in the third polysilicon channel layer 24 c. The firstdopant atom A3 is a dopant atom selected from the group consisting ofhelium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon(Rn) and any combination thereof. The first dopant atom A3 is a dopantatom selected from the group consisting of carbon (C), silicon (Si),germanium (Ge), tin (Sn) and lead (Pb) and any combination thereof. Thefirst dopant atom A3 can be selected from the combination of inert gasesand the IVA group. In the step 63, the first dopant atom A3 is used as asource of dapant to be doped inside the first polysilicon layer 24 a andthe second polysilicon layer 24 b according to the ion implantationmethod.

Then, proceed to the step 64 as shown in FIG. 7F, the first mask 71 isremoved, and the substrate 11 is covered by a second mask 72. The secondmask 72 has a third opening 72 a used for exposing the third polysiliconchannel layer 24 c.

Then, proceed to the step 65 as shown in FIG. 7G, a second dopant atomnot selected from the IIIA group and the VA group A4 is doped inside thethird polysilicon channel layer 24 c to form a first polysilicon channellayer 14. Examples of the second dopant atom A4 include a neutral atom,an inert gas and/or the IVA group. The total doping concentration of thefirst dopant atom A3 and the second dopant atom A4 in the firstpolysilicon channel layer 14 is the same or different with the dopingconcentration of the first dopant atom A3 in the second polysiliconchannel layer 22. For example, the total doping concentration of thefirst dopant atom A3 and the second dopant atom A4 in the firstpolysilicon channel layer 14 is larger than the doping concentration ofthe first dopant atom A3 in the second polysilicon channel layer 22. Thetotal doping concentration of the first dopant atom A3 and the seconddopant atom A4 in the first polysilicon channel layer 14 ranges10¹¹˜10¹⁵ atoms/cm², or is larger than 1012 atoms/cm². The second dopantatom A4 is a dopant atom selected from the group consisting of helium(He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon (Rn) andany combination thereof. The second dopant atom A4 is a dopant atomselected from the group consisting of carbon (C), silicon (Si),germanium (Ge), tin (Sn) and lead (Pb) and any combination thereof. Thesecond dopant atom A4 can also be selected from the combination of inertgases and the IV A group. The first dopant atom A3 and the second dopantatom A4 can be the same or different. In the step 65, the second dopantatom A4 can be used as a source of the dapant to be doped inside thethird polysilicon channel layer 24 c according to the ion implantationmethod. Then, proceed to the step 66 as shown in FIG. 7H, the secondmask 72 is removed.

An OLED display panel and a method of forming a polysilicon channellayer thereof are disclosed in the above embodiments of the invention.The design of disposing a dopant atom not selected from the IIIA groupand the VA group inside the polysilicon layer (such as the polysiliconlayer formed according to the ELA crystallization technology) formed byapplying heat treatment to the crystallization of the amorphous siliconlayer can uniform the defects of the polysilicon layer. Therefore, thenon-uniform crystallization and defect of the polysilicon layer can beimproved, so that the polysilicon channel layer of each pixel TFT hasthe same characteristics. As a result, each pixel TFT has the samecharacteristics, preventing the OLED display panel from generating linemura during operation, largely improving the display quality of the OLEDdisplay panel.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

1. An organic light emitting diode (OLED) display panel, comprising: asubstrate; a pixel disposed on the substrate; and a first thin filmtransistor disposed inside the pixel and comprising a first polysiliconchannel layer, wherein a first dopant atom not selected from the III Agroup and the VA group is doped inside the first polysilicon channellayer.
 2. The panel according to claim 1, wherein the dopingconcentration of the first dopant atom in the first polysilicon channellayer ranges 10¹¹˜10¹⁵ atoms/cm².
 3. The panel according to claim 1,wherein the first thin film transistor further comprises a first gate, afirst source and a first drain, the first source and the first drain arecorrespondingly and electrically connected to two ends of the firstpolysilicon channel layer, the first source is electrically connected toa first constant voltage, and the OLED display panel further comprises:a first scan line and a second scan line both disposed on the substratein parallel; a first data line and a second data line both disposed onthe substrate in parallel, perpendicular to and alternating with thefirst scan line and the second scan line to define the pixel; a secondthin film transistor disposed inside the pixel and comprising a secondgate, a second source, a second drain and a second polysilicon channellayer, wherein the second source and the second drain arecorrespondingly and electrically connected to two ends of the secondpolysilicon channel layer, the second gate is electrically connected tothe first scan line, the second source is electrically connected to thefirst data line, and the second drain is electrically connected to thefirst gate; a storage capacitor disposed inside the pixel, wherein oneend of the storage capacitor is electrically connected between thesecond drain and the first gate, the other end of the storage capacitoris electrically connected between the first source and the firstconstant voltage; and an organic electroluminescent device (OELD)disposed inside the pixel to be electrically connected to the firstdrain and a second constant voltage.
 4. The panel according to claim 3,wherein a second dopant atom not selected from the IIIA group and the VAgroup is doped inside the second polysilicon channel layer.
 5. The panelaccording to claim 4, wherein the first dopant atom and the seconddopant atom are neutral atoms.
 6. The panel according to claim 5,wherein the first dopant atom and the second dopant atom comprise inertgas and/or the IVA group.
 7. The panel according to claim 6, wherein thefirst dopant atom and the second dopant atom respectively are selectedfrom the group consisting of helium (He), neon (Ne), argon (Ar), krypton(Kr), xenon (Xe) and radon (Rn) and any combination thereof. 8 The panelaccording to claim 4, wherein the doping concentration of the firstdopant atom in the first polysilicon channel layer is larger than thedoping concentration of the second dopant atom in the second polysiliconchannel layer.
 9. A method of forming a polysilicon channel layer,comprising: providing a substrate having a first polysilicon layer and asecond polysilicon layer disposed thereon; covering the substrate by afirst mask, wherein the substrate has a first opening for exposing thefirst polysilicon layer; and doping a first dopant atom not selectedfrom the IIIA group and the VA group inside the first polysilicon layerto form a first polysilicon channel layer.
 10. The method according toclaim 9, wherein the doping concentration of the first dopant atom inthe first polysilicon channel layer ranges 10¹¹˜10¹⁵ atoms/cm².
 11. Themethod according to claim 9, further comprising: removing the first maskand covering the substrate by a second mask, wherein the second mask hasa second opening for exposing the second polysilicon layer; and doping asecond dopant atom not selected from the IIIA group and the VA groupinside the second polysilicon layer to form a second polysilicon channellayer, wherein the doping concentration of the second dopant atom in thesecond polysilicon channel layer is the same or different with thedoping concentration of the first dopant atom in the first polysiliconchannel layer.
 12. The method according to claim 11, wherein the firstdopant atom and the second dopant atom are neutral atoms.
 13. The methodaccording to claim 12, wherein the first dopant atom and the seconddopant atom comprise inert gas and/or the IVA group.
 14. The methodaccording to claim 13, wherein the first dopant atom and the seconddopant atom respectively are selected from the group consisting ofhelium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe) and radon(Rn) and any combination thereof.
 15. The method according to claim 14,wherein the doping concentration of the first dopant atom in the firstpolysilicon channel layer is larger than the doping concentration of thesecond dopant atom in the second polysilicon channel layer.
 16. A methodof forming a polysilicon channel layer, comprising: providing asubstrate having a first polysilicon layer and a second polysiliconlayer disposed thereon; covering the substrate by a first mask, whereinthe first mask has a first opening and a second opening for respectivelyexposing the first polysilicon layer and the second polysilicon layer;doping a first dopant atom not selected from the IIIA group and the VAgroup inside the first polysilicon layer and the second polysiliconlayer to respectively form a first polysilicon channel layer and asecond polysilicon channel layer, wherein the doping concentration ofthe first dopant atom in the first polysilicon channel layer is the samewith the doping concentration of the first dopant atom in the secondpolysilicon channel layer; removing the first mask and covering thesubstrate by a second mask, wherein the second mask has a third openingfor exposing the first polysilicon channel layer; and doping a seconddopant atom inside the first polysilicon channel layer to form a thirdpolysilicon channel layer, wherein the total doping concentration of thefirst dopant atom and the second dopant atom in the third polysiliconchannel layer is larger than the doping concentration of the firstdopant atom in the second polysilicon channel layer.
 17. The methodaccording to claim 16, wherein the first dopant atom and the seconddopant atom are neutral atoms.
 18. The method according to claim 17,wherein the first dopant atom and the second dopant atom comprise inertgas and/or the IV A group.
 19. The method according to claim 18, whereinthe first dopant atom and the second dopant atom respectively areselected from the group consisting of helium (He), neon (Ne), argon(Ar), krypton (Kr), xenon (Xe) and radon (Rn) and any combinationthereof.
 20. The method according to claim 16, wherein the total dopingconcentration of the first dopant atom and the second dopant atom in thethird polysilicon channel layer ranges 10¹¹˜10¹⁵ atoms/cm².